The additional delay can be addressed with a structural change to the sampling operation in the sub-ADC. Even if the common mode input voltage does not match the common mode reference voltage, the differential input current remains zero and the common mode input current results in an offset voltage which may be removed through system calibration. Furthermore, no errors are introduced even if the external resistances are not balanced, as long as the common mode input voltage is equal to the common mode reference voltage. Resistances up to 100k, combined with capacitors up to 10μF, may be placed in front of the ADC with less then 0.002% full-scale error (20ppm), while conventional ΔΣ ADCs with the same input network have greater than 10% full-scale errors (100,000ppm). Since the average differential input current is zero, the total error introduced by the external RC network is zero if the resistance tied to the plus/minus inputs of the ADC is balanced. External RC networks applied to the input of the LTC248x simply integrate (average) the input current spikes generated by the ADC. RC networks placed in front of ΔΣ ADCs significantly improve their performance and ease-of-use while providing lowpass and anti-alias filtering. The common mode input current is constant and proportional to the difference between the input common mode voltage and reference common mode voltage. When summed over the entire conversion cycle, the total differential input current is zero, independent of the differential input voltage, common mode input voltage, reference voltage or output code. An innovative front-end sampling architecture controls the switching pattern of the capacitor array. The front-end capacitor switching on a per sample basis is identical to conventional ΔΣ converter sampling. The trick to solving this problem is to take advantage of the oversampling properties of ΔΣ converters. External RC networks that do not completely settle during each sample period cause large DC errors. This pattern is a complex function of the input and reference voltages. A pattern of charging/discharging pulses is seen at the input pin of the ADC. Each time these capacitors are switched to the ADC input, a current pulse is generated. Capacitors are rapidly switched (up to 10MHz) between the input, reference and ground as a function of the final output code. The problem is that the input structure of ΔΣ converters is a switched capacitor network. In order to achieve high resolution, the input is sampled many times during the conversion cycle. The obvious advantage is that it’s much easier to implement a 1-bit converter than a 24-bit converter. Most commercially available ΔΣ converters combine hundreds or even thousands of 1-bit conversions into a single 16-, 20- or 24-bit result. Mike Mayes, in Analog Circuit Design, Volume Three, 2015 How does it work?ĭelta-Sigma converters achieve high resolution by combining many low resolution conversions into one high resolution result. The oscillator pin can be used to adjust the switching frequency, or to externally synchronize the LT1054. The internal oscillator of the LT1054 runs at a nominal frequency of 25kHz. Supply current in shutdown is less than 100μA. The LT1054 can also be shut down by grounding the feedback pin. This output will be regulated against changes in input voltage and output current. By adding an external resistive divider, a regulated output can be obtained. This holds true over the full supply voltage range of 3.5V to 15V. Total voltage loss at 100mA output current is typically 1.1V. An adaptive switch drive scheme optimizes efficiency over a wide range of output currents. It provides higher output current then previously available converters with significantly lower voltage losses. The LT1054 is a monolithic, bipolar, switched-capacitor, voltage converter, and regulator. LT1054 Switched-Capacitor Converter Block Diagram
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